1. Field of the Invention
This invention relates to optimization of the skew of a digital synchronous VLSI system and particularly to the acceleration of operation speed and the reduction of complexity.
2. Description of Related Art
Along with nano-technology that prevails, what is concerned in a high-performance integrated circuit design includes higher design complexity, high-speed clock frequency, lower interconnect width, and lower Supply Voltage, which increases the difficulty of high-performance integrated circuit design. Besides speed and surface area, reliability must be considered for the critical target of optimization.
A high-frequency digital synchronous VLSI circuit operates with a region assembly logic circuit, in this way, registers must be arranged in a specified region of the circuit and are controlled by clock signals; if the digital synchronous circuit is made to operate normally, the clock signals must be transmitted to each of the registers at different time of intervals, and thus the transmission of clock signals is implemented with the aspects of circuit and interconnect.
When a high-speed synchronous circuit gradually raise a clock frequency, the transmission of a clock signal in a Clock Distribution Network is a key point, which may raise clocks of a circuit and may be a feature required by the circuit for normal operation. How to effectively use clock variance for minimization of a clock cycle is a topic for discussion of clock variance scheduling and optimization. The time for the clock signal to reach a register must be corresponding to the limits of zero clocking and double clocking, and thus the circuit may work normally. The time for the clock signal to reach each register is not necessarily synchronous. Thus, effectively using the clock variance may not only make the circuit constantly operate normally but also raise the performance of circuit. Therefore, besides a conventional algorithm of clock variance scheduling and optimization, a conventional algorithm of polynomial time complexity is proposed. Due to the limit of clock cycle, results of multiple clock variation scheduling are given. In this invention, besides the optimization of clock variation scheduling, operation time is also taken seriously so that this invention is practicable.